Balita
Cadence ties with UK design house for 7nm
Starting with a 40nm temperature monitor in 2010, the firm now provides complete process, voltage and temperature (PVT) monitoring blocks as hard IP for processes between 7nm and 40nm. On top of this, it has controller soft IP that provides an interface to multiple PVT blocks across a chip.
It boasts customers in China, France, Germany, Israel, Italy, Japan, Taiwan, South Korea, Russia and the UK, and is a member of TSMC’s Hard IP Alliance.
Moortec-PVT-Architecture-Visio-V7Initially the firm was using Cadence’ Virtuoso analogue custom design flow.
However, this all-analogue approach does not provide an entirely smooth fit for customers designing 16 and 7nm SoCs
“The trend of this class IP design house, is going to 7nm earlier than expected to support end-customer SoC for IoT,” said Cadence product manager David Stratman.
Benign self-interest has driven Cadence to get involved with suppliers of small IP blocks, in order that those small blocks integrate easily on the SoCs being created by Cadence’ larger customers.
“Our engagement with Cadence is a collaboration,” Moortec CTO Oliver King told Electronics Weekly. “Our mutual customers are designing huge SoCs. Cadence supports us to provide what we need to provide so that our mutual customers tape-outs are successful.”
Cadence’ VDI – Virtuoso Digital Implementation – was the answer for Moortec. This is a collection of digital design tools that plug into Virtuoso – offering the same features as their larger digital design tool cousins, but only for designs up to a certain size.
“At 7nm, it improved the seamlessness of the way our IP integrates into the customer’s design flow, and created smaller IP with more optimised timing interfaces,” said Moortec’s King, adding: “It makes it more standard from digital view, so they understand better what we are giving them.”
Nuts and bolts
Moortec’s roots were in analogue design, which was done within Cadence’s Virtuoso tool suite for schematic capture, layout and simulation – initially at 40nm.
More digital content was added to its design flows at each node transition, and the move to a 16nm finfet process prompted Moortec to adopt a more efficient timing-driving digital design methodology, which is when the VDI bundle began to be used – the bundle includes capacity-limited versions of tool such as Genus for RTL synthesis and Innovus for place-and-route.
“These tools and methodologies are then available directly from within the Virtuoso cockpit and designers can move between the analogue and digital domains and view,” according to Cadence’ Stratman.
Subsequently it has added two similar Virtuoso-accessible bundles: Virtuoso Digital Signoff and Virtuoso Digital Test – that include capacity-limited versions of Tempus for static timing analysis, Voltus for digital electro-migration and IR-drop (plus the analogue version Voltus-Fi) and Modus for design-for-test.
Moortec also uses the following digital verification tools: Conformal for equivalence checking, Xcelium for functional verification, Spectre for Spice circuit simulation, Quantus for resistance and capacitance extraction, and Liberate library characterisation tools.
“These integrated digital flows allow Moortec to complete key parts of digital designs at 7nm using non-custom flows, and allows it to better package hard and soft IP components to be integrated into their end customer’s digital SoCs with industry standard files and timing interfaces,” said Stratman.
Moortec’s first 7nm test chip was taped-out in June 2018.
It boasts customers in China, France, Germany, Israel, Italy, Japan, Taiwan, South Korea, Russia and the UK, and is a member of TSMC’s Hard IP Alliance.
Moortec-PVT-Architecture-Visio-V7Initially the firm was using Cadence’ Virtuoso analogue custom design flow.
However, this all-analogue approach does not provide an entirely smooth fit for customers designing 16 and 7nm SoCs
“The trend of this class IP design house, is going to 7nm earlier than expected to support end-customer SoC for IoT,” said Cadence product manager David Stratman.
Benign self-interest has driven Cadence to get involved with suppliers of small IP blocks, in order that those small blocks integrate easily on the SoCs being created by Cadence’ larger customers.
“Our engagement with Cadence is a collaboration,” Moortec CTO Oliver King told Electronics Weekly. “Our mutual customers are designing huge SoCs. Cadence supports us to provide what we need to provide so that our mutual customers tape-outs are successful.”
Cadence’ VDI – Virtuoso Digital Implementation – was the answer for Moortec. This is a collection of digital design tools that plug into Virtuoso – offering the same features as their larger digital design tool cousins, but only for designs up to a certain size.
“At 7nm, it improved the seamlessness of the way our IP integrates into the customer’s design flow, and created smaller IP with more optimised timing interfaces,” said Moortec’s King, adding: “It makes it more standard from digital view, so they understand better what we are giving them.”
Nuts and bolts
Moortec’s roots were in analogue design, which was done within Cadence’s Virtuoso tool suite for schematic capture, layout and simulation – initially at 40nm.
More digital content was added to its design flows at each node transition, and the move to a 16nm finfet process prompted Moortec to adopt a more efficient timing-driving digital design methodology, which is when the VDI bundle began to be used – the bundle includes capacity-limited versions of tool such as Genus for RTL synthesis and Innovus for place-and-route.
“These tools and methodologies are then available directly from within the Virtuoso cockpit and designers can move between the analogue and digital domains and view,” according to Cadence’ Stratman.
Subsequently it has added two similar Virtuoso-accessible bundles: Virtuoso Digital Signoff and Virtuoso Digital Test – that include capacity-limited versions of Tempus for static timing analysis, Voltus for digital electro-migration and IR-drop (plus the analogue version Voltus-Fi) and Modus for design-for-test.
Moortec also uses the following digital verification tools: Conformal for equivalence checking, Xcelium for functional verification, Spectre for Spice circuit simulation, Quantus for resistance and capacitance extraction, and Liberate library characterisation tools.
“These integrated digital flows allow Moortec to complete key parts of digital designs at 7nm using non-custom flows, and allows it to better package hard and soft IP components to be integrated into their end customer’s digital SoCs with industry standard files and timing interfaces,” said Stratman.
Moortec’s first 7nm test chip was taped-out in June 2018.